Nikola Petrovic's starred repositories
RISC-V-CPU
RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
AMBA_AXI_AHB_APB
AMBA bus lecture material
python-qrcode
Python QR Code image generator
torch2chip
Torch2Chip (MLSys, 2024)
awesome-open-hardware-verification
A List of Free and Open Source Hardware Verification Tools and Frameworks
awesome-semiconductor-startups
List of awesome semiconductor startups
verilog_fixed_point_math_library
Fixed Point Math Library for Verilog
18224-s23-tapeout
Build infrastructure for class-wide tapeout for 18-224/624 Intro to Open Source Chip Design, Spring 2023
OpenSERDES
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
awesome-opensource-hardware-repos
List of awesome open source hardware projects
swerv_eh1_fpga
FPGA reference design for the the Swerv EH1 Core
core-v-mcu
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.