pznikola

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

cv32e40s

4 stage, in-order, secure RISC-V core based on the CV32E40P

RISC-V-CPU

RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

corundum

Open source FPGA-based NIC and platform for in-network compute

RTLflow

A GPU acceleration flow for RTL simulation with batch stimulus

essent

high-performance RTL simulator

AMBA_AXI_AHB_APB

AMBA bus lecture material

UberDDR3

Opensource DDR3 Controller

openasip

Open Application-Specific Instruction Set processor tools (OpenASIP)

gem5

The official repository for the gem5 computer-system architecture simulator.

sauria

SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator based on a GeMM systolic array engine.

python-qrcode

Python QR Code image generator

torch2chip

Torch2Chip (MLSys, 2024)

awesome-open-hardware-verification

A List of Free and Open Source Hardware Verification Tools and Frameworks

awesome-semiconductor-startups

List of awesome semiconductor startups

verilog_fixed_point_math_library

Fixed Point Math Library for Verilog

x-heep

eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V

18224-s23-tapeout

Build infrastructure for class-wide tapeout for 18-224/624 Intro to Open Source Chip Design, Spring 2023

OpenSERDES

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

awesome-opensource-hardware-repos

List of awesome open source hardware projects

asic_labs_fa21

asic-labs-fa22

swerv_eh1_fpga

FPGA reference design for the the Swerv EH1 Core

nox

RISC-V Nox core

cv32e40x

4 stage, in-order, compute RISC-V core based on the CV32E40P

core-v-mcu

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

biriscv

32-bit Superscalar RISC-V CPU

FlexASR

FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks