pznikola

AXI4Test

Chisel3 AXI4 memory mapped register

caravel_asic_one

caravel_user_project

https://caravel-user-project.readthedocs.io

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

computer-engineering-resources

A curated list of Computer Engineering resources

dsp-blocks

A collection of common Digital Signal Processing block generators

ethernet-wrapper

Chisel wrapper for Alex Forencich ethernet.

fastvdma

Antmicro's fast, vendor-neutral DMA IP in Chisel

fpga-shells

InterpolatorAndFIRs

ETF students project - Digital signal Interpolation

QueueCIRCT

rocket-chip

Rocket Chip Generator

rocket-chip-fpga-shells

Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards

testchipip

verilog-ethernet

Verilog Ethernet components for FPGA implementation

XiangShan

Open-source high-performance RISC-V processor