Nikola Petrovic's repositories
AXI4Test
Chisel3 AXI4 memory mapped register
Language:Scala000
Language:VerilogApache-2.0000
caravel_user_project
https://caravel-user-project.readthedocs.io
Language:VerilogApache-2.0000
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Language:CBSD-3-Clause000
computer-engineering-resources
A curated list of Computer Engineering resources
CC0-1.0000
dsp-blocks
A collection of common Digital Signal Processing block generators
Language:ScalaApache-2.0000
ethernet-wrapper
Chisel wrapper for Alex Forencich ethernet.
Language:Verilog000
fastvdma
Antmicro's fast, vendor-neutral DMA IP in Chisel
Language:ScalaApache-2.0000
Language:Scala000
InterpolatorAndFIRs
ETF students project - Digital signal Interpolation
Language:Jupyter Notebook000
Language:Makefile000
rocket-chip
Rocket Chip Generator
Language:ScalaNOASSERTION000
rocket-chip-fpga-shells
Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
Language:ScalaApache-2.0000
BSD-3-Clause000
verilog-ethernet
Verilog Ethernet components for FPGA implementation
MIT000
XiangShan
Open-source high-performance RISC-V processor
Language:ScalaNOASSERTION000