Pranav Mittal's repositories

beta-risc

Implementation of Beta Architecture with Reduced Instruction Set Architecture in Verilog

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control-2021

Content for Robo Camp 2021 . Control Systems

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Gringotts-Wizarding-Bank

basic security system using IOT

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analog-function-and-filter

Implemetation of a linear differential equation and filters and various equations in Pspice Orcad

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DS-Traversal

Linked List and Tree Traversal in Memory in Proteus

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breadboard

BreadBoard Implementation examples using BreadBoardSim.exe

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cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

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dma_axi

AXI DMA 32 / 64 bits

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interfaces-Cocotb

interfaces-SiliconMerc created by GitHub Classroom

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job-portal

Connect daily wage worker with opportunities

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mandir

Shri Shivling Triveni Mandir

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PersonalComputer

Bulding a personal computer from scratch , including the software and harware architectture

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