------------------------------ Remark ---------------------------------------- We will be very happy to receive any kind of feedback regarding our tools and cores. We will also be willing to support any company intending to integrate our cores into their project. For any questions / remarks / suggestions / bugs please contact info@provartec.com. ------------------------------------------------------------------------------ Opencores.org project - DMA AXI This core is based on the Provartec PR200 IP - 'Generic High performance dual-core AXI DMA' The original IP is a configurable, generic AXI DMA written in RobustVerilog. This project contains two Verilog cores, one a 32-bit build and the other a 64-bit build. To view the complete IP - http://www.provartec.com/ipproducts/56 - Single channel 32 or 64 bit AXI master DMA core - Supports simultaneous read and write - outstanding AXI commands - command lists ?? - peripheral control - timeouts - endianess swapping?? References : https://github.com/corundum/corundum/blob/master/fpga/common/tb/tx_checksum/test_tx_checksum.py https://opencores.org/projects/dma_axi