J1: a small Forth CPU Core for FPGAs
Rewritten in SystemVerilog from Verilog Source.
ModelSim Altera Starter Edition 10.1d compiles and simulates with unions. Quartus II for Cyclone II FPGA cannot use them. Use this as a workaround.
Forth CPU J1 in SystemVerilog
J1: a small Forth CPU Core for FPGAs
Rewritten in SystemVerilog from Verilog Source.
ModelSim Altera Starter Edition 10.1d compiles and simulates with unions. Quartus II for Cyclone II FPGA cannot use them. Use this as a workaround.
Forth CPU J1 in SystemVerilog