olofk

serv

SERV - The SErial RISC-V CPU

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

edalize

An abstraction library for interfacing EDA tools

corescore

CoreScore

ipyxact

Python-based IP-XACT parser

subservient

Small SERV-based SoC primarily for OpenMPW tapeout

wb_intercon

Wishbone interconnect utilities

fusesocotb

Quick'n'dirty FuseSoC+cocotb example

underserved

qerv

uart16550

UART 16550 core

spi_ram_loader

SPI RAM loader

opentitan

OpenTitan: Open source silicon root of trust

riscv-formal

RISC-V Formal Verification Framework

zipcpu

A small, light weight, RISC CPU soft core

Booth_Multipliers

Parameterized Booth Multiplier in Verilog 2001

openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

riscv-opcodes

RISC-V Opcodes

basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

hossein1387.github.io

Personal Website

keball

Regardless if you are 13 years old or retired, you might want to run keball

olofk.github.io

prince

The Prince lightweight block cipher in Verilog.

qspiflash

A set of Wishbone Controlled SPI Flash Controllers

salsa20

Sals20 Stream Cipher core in Verilog

subservient_gfmpw1

https://caravel-user-project.readthedocs.io

subtest

tt02-serv

usbcorev

A full-speed device-side USB peripheral core written in Verilog.