olofk

serv

SERV - The SErial RISC-V CPU

edalize

An abstraction library for interfacing EDA tools

corescore

CoreScore

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

fusesocotb

Quick'n'dirty FuseSoC+cocotb example

ipyxact

Python-based IP-XACT parser

underserved

olofk.github.io

wb_intercon

Wishbone interconnect utilities

opentitan

OpenTitan: Open source silicon root of trust

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

uart16550

UART 16550 core

qerv

riscv-formal

RISC-V Formal Verification Framework

prince

The Prince lightweight block cipher in Verilog.

subtest

subservient_gfmpw1

https://caravel-user-project.readthedocs.io

riscv-opcodes

RISC-V Opcodes

keball

Regardless if you are 13 years old or retired, you might want to run keball

subservient

Small SERV-based SoC primarily for OpenMPW tapeout

hossein1387.github.io

Personal Website

spi_ram_loader

SPI RAM loader

basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

tt02-serv

openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

zipcpu

A small, light weight, RISC CPU soft core

qspiflash

A set of Wishbone Controlled SPI Flash Controllers

usbcorev

A full-speed device-side USB peripheral core written in Verilog.

salsa20

Sals20 Stream Cipher core in Verilog

Booth_Multipliers

Parameterized Booth Multiplier in Verilog 2001