Olof Kindgren's repositories
fusesocotb
Quick'n'dirty FuseSoC+cocotb example
wb_intercon
Wishbone interconnect utilities
cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
riscv-formal
RISC-V Formal Verification Framework
prince
The Prince lightweight block cipher in Verilog.
subservient_gfmpw1
https://caravel-user-project.readthedocs.io
riscv-opcodes
RISC-V Opcodes
keball
Regardless if you are 13 years old or retired, you might want to run keball
subservient
Small SERV-based SoC primarily for OpenMPW tapeout
hossein1387.github.io
Personal Website
spi_ram_loader
SPI RAM loader
basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
qspiflash
A set of Wishbone Controlled SPI Flash Controllers
usbcorev
A full-speed device-side USB peripheral core written in Verilog.
salsa20
Sals20 Stream Cipher core in Verilog
Booth_Multipliers
Parameterized Booth Multiplier in Verilog 2001