miaochenlu

awesome-chatgpt-prompts

This repo includes ChatGPT prompt curation to use ChatGPT better.

paper-reading

深度学习经典、新论文逐段精读

zh-google-styleguide

Google 开源项目风格指南 (中文版)

pyautogui

A cross-platform GUI automation Python module for human beings. Used to programmatically control the mouse & keyboard.

OpenBLAS

OpenBLAS is an optimized BLAS library based on GotoBLAS2 1.13 BSD version.

VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

bpf-developer-tutorial

eBPF Developer Tutorial: Learning eBPF Step by Step with Examples

perf-book

The book "Performance Analysis and Tuning on Modern CPU"

amx

Apple AMX Instruction Set

gemmini

Berkeley's Spatial Array Generator

Loser-HomeWork

卢瑟们的作业展示，答案讲解，以及一些C++知识

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

LLVM_for_cpu0

This is a tutorial to learn LLVM, I realize a backend to compiler machine code for cpu0 which is a simple RISC cpu.

vicuna

RISC-V Zve32x Vector Coprocessor

AIGC_Resources

Gather AIGC most useful tools, materials, publications and reports

sv-tutorial

SystemVerilog Tutorial

t1

simdtutor

x86-64 SIMD矢量优化系列教程

wake

The SiFive wake build tool

VexiiRiscv

Like VexRiscv, but, Harder, Better, Faster, Stronger

rvv-bench

A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code

riscv-matrix-extension-spec

A matrix extension proposal for AI applications under RISC-V architecture

AMX-Guide

Advanced Matrix Extensions (AMX) Guide

Verilog-SystemVerilog-Guide

Verilog/SystemVerilog Guide

labs-with-cva6

Advanced Architecture Labs with CVA6

intel-training-modules

systemc-common-practices

SystemC Common Practices (SCP)

riscv-dv

Random instruction generator for RISC-V processor verification

minimal-diplomacy

Example of Chisel3 Diplomacy

rocket-chip

Rocket Chip Generator