Giters
vproc
/
vicuna
RISC-V Zve32x Vector Coprocessor
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Stargazers:
154
Watchers:
6
Issues:
100
Forks:
45
vproc/vicuna Issues
How to Handle conv + bias in conv_3x3 for input(int8) * weight(int8) + bias(int32)?
Updated
2 months ago
Illegal configuration created by config.mk
Updated
6 months ago
Comments count
2
Applications hang indefinitely on Verilator when size of data cache is different than 0
Updated
8 months ago
Comments count
1
Machine mode CSRs not accessible with Ibex host core when using Vicuna's verilated model
Updated
8 months ago
Comments count
1
Certain applications when executed with dual and triple pipeline configurations on verilated model of Vicuna hang indefinittely
Updated
10 months ago
Reserved word not implemented: 'config'
Closed
a year ago
Comments count
1
Error in Questasim Simulation
Updated
a year ago
'Illegal Instruction' when executing sign and zero extend functions when destination LMUL=8
Updated
a year ago
vzext.vf2 instruction execution problem
Updated
a year ago
Comments count
4
Combinatorial Loop Alert while Generating bitstream for vicuna using CV32E40X as a scalar core
Updated
a year ago
Floating point support.
Updated
2 years ago
Vicuna accepts instructions for which source registers are not valid.
Closed
2 years ago
fail to set VREG_W=2048
Closed
2 years ago
Comments count
2
No way to clear a cache error?
Updated
2 years ago
Vicuna + Ibex and WFI
Updated
2 years ago
narrowing instructions are never popped from the instruction queue
Updated
2 years ago
Comments count
1
Wrong operand for `vwmacc(u|us|su).vx`
Updated
2 years ago
Wrong result generated by multiply unit (probably control logic related)
Updated
2 years ago
Comments count
1
Masking not working
Updated
2 years ago
`vslidedown.(vx|vi)` issue when VLMAX is exceeded
Updated
2 years ago
Tail-undisturbed policy violation for comparison instructions.
Updated
2 years ago
Rounding issue for `vasub(u).(vv|vx)`
Updated
2 years ago
Question about alignment and SRecord
Closed
2 years ago
Comments count
2
Suggestion for vectorizing MaxPool and Convolution Layer
Updated
2 years ago
Comments count
1
Signal stability issue on result interface
Closed
2 years ago
Comments count
4
question about test.c
Closed
2 years ago
Comments count
4
Error in Synthesizing the vicuna on Genesys2 board
Updated
2 years ago
Comments count
4
Missing memory and result transaction for memory instruction
Closed
2 years ago
Comments count
5
Asking for help about extending MEM_W to 64 bit
Closed
2 years ago
Comments count
1
`instr_notspec_d` signal gets updated even for illegal instructions (causing infinite stall)
Closed
2 years ago
Comments count
8
Measuring run time of C codes in normal and vector mode
Closed
2 years ago
Comments count
10
Adding custom configuration to config.mk file
Closed
2 years ago
Comments count
10
Rare infinite stall triggered by a specific delay constellation during memory transactions
Updated
2 years ago
Comments count
1
Verilator problem in simulating added custom config
Updated
2 years ago
Thanks for the documentation
Closed
2 years ago
Result transaction id and data issue (when `result_ready` has random delay)
Closed
2 years ago
Comments count
5
Missing result transaction when commit transactions are randomly delayed
Closed
2 years ago
Comments count
2
vrgather.vv issue (possible control signal issue in vproc_elem)
Closed
2 years ago
Comments count
3
Bug in Verilator simulation
Closed
2 years ago
Comments count
3
vredsum problem even after alignment issue is solved
Closed
2 years ago
Comments count
1
Tail-agnostic policy violation for mask instruction
Updated
2 years ago
Comments count
1
Vector multipilication output is incorrect
Closed
2 years ago
Comments count
6
Coprocessor stalls indefinitely if core issues random memory result transactions
Closed
2 years ago
Comments count
4
[Question] Data cache configuration in demo_top
Closed
2 years ago
Comments count
2
Question about vicuna simulation directory
Closed
2 years ago
Comments count
12
Syntax error in vproc_config generation
Closed
2 years ago
Comments count
7
C code simulation using Verilator
Updated
2 years ago
Comments count
6
RAM_ASIC register file has multiply driven registers
Updated
2 years ago
Comments count
2
cv32e40x_lsu_response_filter missing in gen_demo.tcl
Closed
2 years ago
Comments count
1
riscv-gnu-toolchain dropped the rvv-intrinsic branch
Closed
2 years ago
Comments count
1
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