jideoyelayo1 / PongGameVerilog

A Pong Game made in Verilog

Geek Repo:Geek Repo

Github PK Tool:Github PK Tool

PongGame

Image

PongGame is a classic arcade game developed using Verilog with Vivado 2021.2 for Nexys 4DDR. The game is a single player Ping Pong game that displays the score on the VGA out and uses buttons to move around.

Gameplay

The objective of the game is to score points by hitting the ball with your paddle and preventing the ball from hitting your side of the screen. The game ends when one player reaches a score of 9. The score counter for each player is displayed on the screen.

Prerequisites

To run the game, you will need the following:

  • Nexys 4DDR board
  • VGA monitor
  • Vivado 2021.2 software

Installation

To install and run the game, you can follow these steps:

  • Clone the repository to your local machine.
  • Open the project in Vivado 2021.2.
  • Generate a bitstream and program the Nexys 4DDR board.
  • Connect the VGA monitor to the board.
  • Power on the board and start playing!

Controls

The game can be played using the following controls:

  • Use the buttons on the board to move your paddle up and down.
  • The score counter for each player is displayed on the screen.

Features

  • Single player Ping Pong game
  • Displays the score on VGA out
  • Uses buttons to move around
  • Score counter counts to 9 for each player

Improvements

Some improvements that could be made to the game are:

  • Add sound effects and background music
  • Improve the UI by adding more colors and visual elements
  • Add more game modes and difficulty levels

License

This project is licensed under the MIT License. See the LICENSE file for details.

Contributing

Contributions to the project are welcome. To contribute, please follow these steps:

  • Fork the repository.
  • Create a new branch for your feature or bug fix.
  • Make your changes and commit them.
  • Push your changes to your forked repository.
  • Submit a pull request to the main repository.

About

A Pong Game made in Verilog

License:MIT License


Languages

Language:SystemVerilog 37.2%Language:Verilog 20.1%Language:Tcl 14.8%Language:Shell 12.7%Language:JavaScript 6.6%Language:VHDL 3.5%Language:C 3.1%Language:Stata 1.1%Language:Batchfile 0.6%Language:Forth 0.1%Language:Pascal 0.1%