Giters

jaytlang / risc-y

Six stage RISC-V processor supporting the RV32I instruction set

Repository from Github https://github.comjaytlang/risc-yRepository from Github https://github.comjaytlang/risc-y

risc-vbluespec

risc-y

Six-stage processor supporting the RV32I instruction set, written from scratch in Bluespec. Final design project submission for MIT 6.004, and a continuous work in progress since.

About

Six stage RISC-V processor supporting the RV32I instruction set

risc-vbluespec

Languages

Language:C 33.0%Language:Assembly 20.2%Language:Bluespec 19.4%Language:Python 17.6%Language:C++ 5.0%Language:Shell 2.7%Language:Makefile 2.1%