jakubcabal / spi-fpga

SPI master and SPI slave for FPGA written in VHDL

jakubcabal/spi-fpga Issues

Maximum SCLK frequency on SPI SLAVE module
Updated 10 months ago1
spi slave miso test
Closed 2 years ago1
spi slave in hw => dout_vld no creating '1' value
Closed 2 years ago4
Question: spi slave sim with just master => slave mosi data transfer
Closed 2 years ago4
Support for different transfer size
Closed 3 years ago2
Possible Meta-Stability Issue in Slave Module
Closed 3 years ago1
A question about sclk edge
Closed 5 years ago4
Not working on Cyclone II
Closed 5 years ago7