Giters

jakubcabal / spi-fpga

SPI master and SPI slave for FPGA written in VHDL

Geek Repo:Geek Repo

Github PK Tool:Github PK Tool

Support for different transfer size

keesj opened this issue · comments

commented

Hi,

I have experimented with your code a little. I find it nice to read and learn from. For my purpose I need a larger transfer size (16 bits) perhaps that support for common transfer size (8,16,24,32) can be added?

commented

Hi, I plan to add support for different transaction sizes in the next version (perhaps this month) as VHDL generic.