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jakubcabal / spi-fpga

SPI master and SPI slave for FPGA written in VHDL

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Question: spi slave sim with just master => slave mosi data transfer

imuguruza opened this issue · comments

commented

Hi!

I am trying to simulate just a master to slave data transfer through MOSI where the slave transfer nothing to the master.
I was wondering if that's OK, I am trying to usethe SPI_MASTER procedure to generate the SPI waveforms, but I see nothing.

I was wondering if I misundertood some part of the code.
Thanks!

commented

Hi, that configuration should work. But without your source code, I can't tell where the error is.

commented

Hi, I have finally managed it, for the record, I have commented out the next processes:

And I have used the procedude SPI_MASTER to generate data transmission, this line.

I want to add two things:

  • I find confusing how the SPI and mdi / mdo are used. I believe they are swapped. For example, here. If it's MOSI the assigned data should be MDO right?

  • Running the simulation, I still see that the line MISO generates signal, and I don't understand why is happening that... The TB I am running is the following: https://gist.github.com/imuguruza/9d347bcb641aa9bab0856d5de4ba7e0f

The SPI slave is wrapped around a top.vhd where some additional stuff is done with the received data from SPI.

Running the TB, I see the following waveforms:

image

Any idea why miso is driving a signal, when I am not using it in the TB?

commented

Hi, to your questions:

  • SMM_MDI signal of the procedure SPI_MASTER is used to receive (therefore DI) user data into the SPI_MASTER model (procedure). The SPI_MASTER then sends this data via the MOSI signal. But it probably deserves a clearer name.
  • SPI_SLAVE has a common shift register for both received and sent data. Therefore, if the user does not write data to SPI_SLAVE to send to SPI_MASTER, SPI_SLAVE will start sending (via MISO) the last received data. This should be eliminated by constant setting of some port SPI_SLAVE: DIN_VLD => '1', DIN => (others => '0').
commented

SMM_MDI signal of the procedure SPI_MASTER is used to receive (therefore DI) user data into the SPI_MASTER model (procedure). The SPI_MASTER then sends this data via the MOSI signal. But it probably deserves a clearer name.

I see

SPI_SLAVE has a common shift register for both received and sent data. Therefore, if the user does not write data to SPI_SLAVE to send to SPI_MASTER, SPI_SLAVE will start sending (via MISO) the last received data. This should be eliminated by constant setting of some port SPI_SLAVE: DIN_VLD => '1', DIN => (others => '0').

Ok, I have tried it out and now I see nothing in MISO.
Thanks!