j054n's starred repositories

IoT-For-Beginners

12 Weeks, 24 Lessons, IoT for All!

blockchain-demo

A web-based demonstration of blockchain concepts.

Language:PugLicense:MITStargazers:5141Issues:245Issues:45

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

Language:VerilogLicense:ISCStargazers:2955Issues:165Issues:176

learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V

Language:C++License:BSD-3-ClauseStargazers:2460Issues:82Issues:74

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Language:VerilogLicense:BSD-3-ClauseStargazers:1975Issues:88Issues:40

riscv

RISC-V CPU Core (RV32IM)

Language:VerilogLicense:BSD-3-ClauseStargazers:1155Issues:50Issues:18

Cores-VeeR-EH1

VeeR EH1 core

Language:SystemVerilogLicense:Apache-2.0Stargazers:793Issues:57Issues:99

RWTS-PDFwriter

An OSX print to pdf-file printer driver

Language:ShellLicense:GPL-2.0Stargazers:771Issues:25Issues:42

pp4fpgas

Parallel Programming for FPGAs -- An open-source high-level synthesis book

Language:TeXLicense:CC-BY-4.0Stargazers:768Issues:55Issues:17

BNN-PYNQ

Quantized Neural Networks (QNNs) on PYNQ

Language:Jupyter NotebookLicense:BSD-3-ClauseStargazers:658Issues:52Issues:149

vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Language:JavaScriptLicense:GPL-3.0Stargazers:525Issues:22Issues:431

CFU-Playground

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.

Language:VerilogLicense:Apache-2.0Stargazers:455Issues:29Issues:213

arduino-create-agent

The Arduino Create Agent

Language:GoLicense:AGPL-3.0Stargazers:417Issues:36Issues:333

Cores-SweRVolf

FuseSoC-based SoC for SweRV EH1

nightminer

Simple Python CryptoCurrency mining client

Language:PythonLicense:MITStargazers:197Issues:25Issues:14

audiostream

Audio API for streaming raw data to speakers

Language:PythonLicense:MITStargazers:188Issues:30Issues:40

riscv-simple-sv

A simple RISC V core for teaching

Language:SystemVerilogLicense:BSD-3-ClauseStargazers:160Issues:3Issues:3

RISC-V-Processor

Verilog implementation of multi-stage 32-bit RISC-V processor

Language:VerilogStargazers:60Issues:4Issues:0

GRBL_STM32

An open source, embedded, high performance g-code-parser and CNC milling controller written in optimized C that will run on a straight STM32F7X

AWS-F1-Developer-Labs

AWS F1 Xilinx Developer Labs

Language:C++Stargazers:27Issues:0Issues:0

movement

Using Smartphones to Encourage Movement

Language:Jupyter NotebookStargazers:21Issues:3Issues:0

firmware-nordic-thingy91

Edge Impulse firmware for Nordic Thingy91

Language:CLicense:Apache-2.0Stargazers:12Issues:14Issues:2

riscv-simple

Computer architecture learning environment using FPGAs

Language:AssemblyLicense:NOASSERTIONStargazers:11Issues:2Issues:0

vscode-verilog

A Fork of the Verilog Runner Extension for VSCode

Language:TypeScriptLicense:MITStargazers:4Issues:1Issues:0

CNC_ControlPanel

CNC Control Panel project built for Element 14 Presents.

Language:C++Stargazers:2Issues:0Issues:0

veril

A tiny bitcoin miner written in SystemVerilog, tested with Arty S7 50 FPGA

Language:SystemVerilogLicense:GPL-3.0Stargazers:1Issues:0Issues:0