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chipsalliance
/
Cores-VeeR-EH1
VeeR EH1 core
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Issues:
99
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chipsalliance/Cores-VeeR-EH1 Issues
Has the maintenance of this repository been stopped?
Updated
3 months ago
Comments count
1
extension `zicsr' required
Updated
3 months ago
tcl file
Updated
3 months ago
Instruction after pmpaddr0 csr write was not executed
Closed
9 months ago
Comments count
7
Not generate waveform when using vcs to test Hello World.
Updated
10 months ago
Comments count
2
coremark/dhrystone testing can't get 4.9 CM/MHz with rtl simulation or in FPGA
Updated
a year ago
The new feature of verilator stops building procession
Updated
a year ago
Comments count
2
OpenOCD download to ICCM/DCCM failed.
Closed
2 years ago
Comments count
1
Blocking Loads/DMA disable
Updated
2 years ago
Repo renaming
Closed
2 years ago
Comments count
2
Coremark for new extension
Updated
2 years ago
facing issues when C code size goes beyond 8KB
Updated
2 years ago
Comments count
1
Question about pipeline FF enable signals
Updated
2 years ago
Fusesoc's sim target is deprecated
Closed
3 years ago
Comments count
10
GHR refresh
Updated
3 years ago
Comments count
1
Formal Verification of SweRV EH1 using riscv-formal
Closed
3 years ago
CoreMark test score
Closed
3 years ago
Comments count
2
Usage scenarios of different DFFs
Updated
3 years ago
Unable to replicate performance improvement achieved by using different target values
Updated
3 years ago
Comments count
1
Try running multi thread program on swerv EH1 core
Closed
3 years ago
Comments count
2
openocd timeout occurs when trying to load elf file using command 'load_image'.
Closed
3 years ago
Comments count
7
fpga_optimize cannot be set to 0 in swerv_config
Updated
3 years ago
Comments count
1
slip in dec_decode_ctrl
Closed
3 years ago
Timing violations with Vivado
Closed
3 years ago
Comments count
4
$readmem file address beyond bounds of array
Closed
3 years ago
Comments count
8
GCC version in Makefile
Closed
3 years ago
Comments count
4
cmark_dccm fails to build
Closed
4 years ago
Comments count
3
tlu_flush_path_e4
Updated
4 years ago
Comments count
7
Set default mrac value with swerv.config
Updated
4 years ago
Comments count
1
Can I integrate the Cores-SweRV on Zedboard fpga?
Closed
4 years ago
Comments count
1
Macro definitions not being found
Closed
4 years ago
Comments count
2
dccm initialization
Closed
4 years ago
Comments count
3
$readmem file address beyond bounds of array
Closed
4 years ago
Comments count
6
The CSR mepc cann't save correct mret address after Continuous NMI happened
Closed
4 years ago
Comments count
23
NMI HELP
Closed
4 years ago
Comments count
1
print instruction to exec.log
Closed
4 years ago
Comments count
2
which unit control flushing of the pipelines?
Closed
4 years ago
Comments count
3
No tags for releases
Closed
4 years ago
Comments count
5
How can I debug using Verilator and gdb
Closed
4 years ago
Comments count
6
Stall point
Closed
4 years ago
Comments count
5
Delay after fetching instructions when not using icache
Closed
4 years ago
Comments count
4
question about adding custom instructions
Closed
4 years ago
Comments count
2
Speculative load observed on LSU AXI
Closed
4 years ago
Comments count
10
mcontrol chain bit not WARL on triggers 1 & 3
Closed
4 years ago
Comments count
3
typo in swerv.config
Closed
4 years ago
Comments count
4
pic
Closed
4 years ago
Comments count
5
Which signal should I choose to trace Load/Store/pipeline state
Closed
4 years ago
Comments count
1
Cores-SweRV development planning
Closed
4 years ago
Comments count
8
Erasing pending bits for interrupts
Closed
4 years ago
Comments count
25
Determine size of i-cache
Closed
4 years ago
Comments count
2
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