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iBug / adc_lab

Projects for course <Analog & Digital Circuits Lab>

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vivadoverilogdigital-circuits

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Projects for course <Analog & Digital Circuits Lab>

vivadoverilogdigital-circuits

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Language:VHDL 87.7%Language:SystemVerilog 8.4%Language:Verilog 3.2%Language:Coq 0.6%Language:Pascal 0.1%Language:Tcl 0.0%