hutch31

sv2chisel

(System)Verilog to Chisel translator

gpt-engineer

Specify what you want it to build, the AI asks for clarification, and then builds it.

microecc

protocol

An ASCII Header Generator for Network Protocols

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

gsn2x

Tool to create graphical representations of Goal Structuring Notations from YAML.

vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

easysoc-diagrammer

Layout, rendering ELK Graph generated by easysoc-firrtl, and display the graph as an interactive diagram to represent Chisel generated Firrtl circuits.

ip-contributions

For contributions of Chisel IP to the chisel community.

proton

swerv_eh1

A directory of Western Digital’s RISC-V SweRV Cores

chisel-aes

Chisel implementation of AES

fwrisc

Featherweight RISC-V implementation

tiny-ECDH-c

Small portable Elliptic-Curve Diffie-Hellman in C

nfmac10g

Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC

verilog-ethernet

Verilog Ethernet components for FPGA implementation

ansible-playbooks

Playbooks for configuring CIC Workstations and Servers

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

eve-wspace

Wormhole mapping and corporation management for Eve Online.

chisel2-deprecated

trivium

different implementations of the trivium stream-cipher

migen

A Python toolbox for building complex digital hardware

verilog-utils

native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches

steam-for-linux

Issue tracking for the Steam for Linux beta client

sdlib

srdy-drdy library

tv80

TV80 Z80-compatible microprocessor

MACsec-Test-Vectors

vpi_pcap_dump

Dump packets from Verilog to a pcap file using VPI calls from simulator

c2verilog

Inofficial version of c-to-verilog.com

System-Verilog-Packet-Library

System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers