gatecat

nextpnr-xilinx

Experimental flows using nextpnr for Xilinx devices

prjoxide

Documenting Lattice's 28nm FPGA parts

meowality

nextpnr-xilinx-meta

Metadata for the nextpnr-xilinx xc7 flow

openvtx

Emulator for VT168 etc

mistral-test

emu293

emu293 SPG293 emulator and associated tooling

fabulous-mpw2-bringup

fabulous-tapeout-automation

one_hot_fpga_gf180

FPGA with a custom SRAM+mux bitcell for onehot routing

litex

Build your hardware, easily!

prjoxide-db

prjoxide database

coriolis

Coriolis VLSI EDA Tool (LIP6)

fabulous_mpw0gf

fabulous efpga tapeout on gf180

litex-boards

LiteX boards files

mister_nes_gfmpw1

nextpnr

nextpnr portable FPGA place and route tool

OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow

caravel_board

FABulous

Fabric generator and CAD tools

fabulous_mpd

Example digital project for the Efabless Caravel "openframe" harness

mapnik

Mapnik is an open source toolkit for developing mapping applications

one-hot-fpga-gf180-3x3

3x3 variant to be less demanding on precheck

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

openstreetmap-carto

A general-purpose OpenStreetMap mapnik style, in CartoCSS

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

pythondata-cpu-cv32e40p

Python module containing system_verilog files for cv32e40p cpu (for use with LiteX).

riscv-dbg

RISC-V Debug Support for our PULP RISC-V Cores

scratching-post

sky130_klayout_pdk

Skywaters 130nm Klayout PDK