g578g

g578g

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awesome-chatgpt-prompts

This repo includes ChatGPT prompt curation to use ChatGPT better.

Language:HTMLLicense:CC0-1.0Stargazers:111230Issues:1437Issues:0

opentitan

OpenTitan: Open source silicon root of trust

Language:SystemVerilogLicense:Apache-2.0Stargazers:2526Issues:105Issues:6744

Accelerating-CNN-with-FPGA

This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.

Language:C++License:NOASSERTIONStargazers:721Issues:23Issues:7

Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

Language:PythonLicense:Apache-2.0Stargazers:616Issues:42Issues:92

CuteHMI

CuteHMI is an open-source HMI (Human Machine Interface) software written in C++ and QML, using Qt libraries as a framework. GitHub repository is a mirror!

Language:C++License:MITStargazers:222Issues:21Issues:1

ARM9-compatible-soft-CPU-core

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

Language:VerilogLicense:Apache-2.0Stargazers:73Issues:5Issues:3

Performance-comparison-of-GAN-on-cifar-10

Performance comparison of ACGAN, BEGAN, CGAN, DRAGAN, EBGAN, GAN, infoGAN, LSGAN, VAE, WGAN, WGAN_GP on cifar-10

Language:PythonLicense:MITStargazers:37Issues:3Issues:3

i2c_slave

I2C slave Verilog Design and TestBench

Language:CStargazers:12Issues:0Issues:0

VHDL-Communications

Example code showing different communications such as TTL, SPI and I2C.

Language:VHDLLicense:Apache-2.0Stargazers:10Issues:3Issues:0

Zynq-TX-UTT

Hardware acceleration: performance evaluation of the Xilinx Zynq-7000 SoC ZC702

Language:VHDLLicense:GPL-3.0Stargazers:5Issues:4Issues:0

vhdl-neuralnet

Feedforward neural network with custom hardware acceleration

Design_of_Computer_Systems

Designing Pipelined RISC Processor

Language:VerilogStargazers:3Issues:1Issues:0

ImageProcessorCore

Image processor core for hardware acceleration of image processing

Language:SystemVerilogLicense:GPL-3.0Stargazers:2Issues:3Issues:0

HardwareAcceleration

Accelerate sign algorithm through FGPA

Language:VerilogStargazers:2Issues:4Issues:0

HardwareLSTM

Implementing hardware acceleration techniques on the feed forward path of an LSTM neural network

fpga-pong

Automatically exported from code.google.com/p/fpga-pong

Language:VerilogStargazers:1Issues:1Issues:0

comp16

A 16-bit fpga microcomputer - 50 Mhz, 128 kB RAM, text VGA output, serial port, PS/2 Interface, and a RISC-ish design

Language:VerilogLicense:GPL-3.0Stargazers:1Issues:0Issues:0

MIPS-PIPELINE_FPGA

Implementação do caminho de dados MIPS com Pipeline em um FPGA Altera DE2-115

Language:VerilogLicense:GPL-3.0Stargazers:1Issues:2Issues:0

CNN.CompAcc

CNN compression and acceleration with algorithms and hardware design

Language:VerilogStargazers:1Issues:1Issues:0