franout / DLX_project

Deluxe RISC processor

DeLuXe RISC processor project

RISC processor architecture designed by John L. Hennessy and David A. Patterson.

Microelectronic System course (MsC in Embedded Systems Engineering) @ Polythecnic of Turin, Italy

Table of Contents

• Setup
• Architecture
• Software
• Simulation
• Synthesis
• Layout
• Tests
• Documentation
• License

Clone

Clone this repo to your local machine using and feel free to contribute!

$ git clone https://github.com/franout/DLX_project.git

Setup

You need to have installed a HDL simulator tool (for the simulation) and a synthesis tool (in case you want to synthesize the design). In this project Questa Sim 10.7 and Design Compiler have been used.

Architecture

The DLX is essentially a cleaned up (and modernized) simplified MIPS CPU. The DLX has a simple Big Endian 32-bit load/store pipelined architecture, somewhat unlike the modern MIPS CPU.

• DLX top level entity

• Customizable hardware parameters (pre-synthesis)

  • IR size, bitwidth of Instruction Register
  • PC size, bitwidth of Program Counter

Software

For creating creating the hex dump file to be used in the simulation (loaded in the Instruction Data Ram):

  $ ./software/assembler.sh {ASM_FILE_PATH}

The produced hexadecimal file should be copied in the memories folder.

Moreover, in the memories folder it is present also a python script for generating random data suitable for the DRAM.

  $ ./hardware/dlx/test_bench/memories/generate_random_values_dram.py

Simulation

For exectuting the simulation of the DLX, it is necessary to execute:

  $ ./scripts/simulation.sh

It will compile the needed files for executing the simulation. Moreover, there are two types of simulations, one with the Universal Verification Methodology architecture and the other one with the normal configuration (IRAM-DLX-DRAM).

Synthesis

For executing the synthesis of the DLX:

  $ ./scripts/synthesis.sh

It will execute different synthesis with different clocks (starting from unconstrained design) and area footprint. Moreover, it will be synthesized taking into account a possible Scan chain (DfT) for a further production phase.

Layout

For executing the physical design of the synthesized DLX:

  $ ./scripts/physical_design.sh gui/no_gui

It will execute the physical desing of differt design point ( for different clock values and area).

Tests

For functionally verify the microprocessor refers to the testbench in System Verilog. They are divided for each stage and control unit for regression test

  $ ./scripts/regression_test.sh

Documentation

For a more detailed information see Wiki's project.

Useful Link

Reach out to me at one of the following places!

• System Verilog Tutorial
• System Verilog Tutorial 2
• Model Sim User Manual
• Overflow of binary numbers
• Universal Verification Methodology tutorial

License

GNU General Public License v3.0