Francesco Angione (franout)

franout

Geek Repo

Location:Torino

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cad-polito-it

Francesco Angione's repositories

tensorflow_for_pynqz2

tensorflor 2.1 wheel for pynq z2 ( zynq 7000 xilinx SoC ), cross compiled with different compiler's flags using the script provided by tensorflow for building it for rasberry

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DLX_project

Deluxe RISC processor

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Cogitantium

Hardware Accelerator for ML

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arm-tutorial-rpi

Raspberry-Pi Bare Metal Tutorial

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CTH_HPC

High parallel computing @ Chalmers University of technology

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docker-centos

Docker recipe to build a CentOS GNU/Linux image

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DPL_termometer

Implementation of a termometer

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FPU

IEEE 754 floating point unit in Verilog

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fpuvhdl

Floating Point Adder and Multiplier

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HDFIT

HDFIT (Hardware Design Fault Injection Toolkit) Github documentation pages.

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hw

RTL, Cmodel, and testbench for NVDLA

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misc_3d_draw

A repository for miscellaneous 3D drawing

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SixtySecondsCV

SixtySecondsCV

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FreeRTOS-Kernel

FreeRTOS kernel files only, submoduled into https://github.com/FreeRTOS/FreeRTOS and various other repos.

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HDFIT.ScriptsHPC

This repository contains an HPC (High Performance Computing) reliability benchmark, carrying out fault injection experiments on a variety of HPC applications, targeting BLAS (Basic Linear Algebra Subroutines) GEMM (GEneral Matrix Multiply) operations.

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opendcdiag

OpenDCDiag is an open-source project designed to identify defects and bugs in CPUs. It consists of a set of tests built around a sophisticated CPU testing framework.

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SystemVerilogReference

training labs and examples

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tensorflow

An Open Source Machine Learning Framework for Everyone

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Testing_and_fault_tolerance

Testing_fault_tolerance

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vcddiff

Basic VCD comparison tool, for Verilator testing

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verilator

Verilator open-source SystemVerilog simulator and lint system

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