fischermoseley / manta

A configurable and approachable tool for FPGA debugging and rapid prototyping.

https://fischermoseley.github.io/manta/

fischermoseley/manta Issues

help with 'Only got 0 out of 7 bytes'
Closed 4 months ago2
Not enough bytes received during Logic Analyzer capture
Updated 4 months ago6
Reference examples in documentation site
Updated 4 months ago
Port examples to the Nexys Video
Updated 4 months ago
Yosys-compatible verilog
Closed 5 months ago2
Switch from Scapy to builtin Python sockets library
Closed 6 months ago
Refactor block_memory addressing scheme to not use modulo operator
Closed 6 months ago
Re-add some Logic Analyzer core features
Closed 6 months ago
Add method for dumping logic analyzer contents to Python
Closed 6 months ago
Convert block_memory address/data/write enable arrays to unpacked
Closed 6 months ago
Re-add some IO core features
Closed a year ago
Fix Ethernet packet format
Updated a year ago