Refactor block_memory addressing scheme to not use modulo operator

[Fischer Moseley]

Right now the block_memory module implements an arbitrarily sized block memory as $N$ 16-bit BRAMs in parallel. This is totally fine, but these are mapped into Manta's internal memory space such that the entires are interleaved - which requires a few modulo and division operators that totally wreck the timing performance when large inputs are used.

Instead of interleaving each core's address space, Manta could just place each 16-bit wide BRAM in address space sequentially.

As an example, a 34-bit wide BRAM would presently be mapped onto Manta's internal bus as:

Bus Address Space	BRAM Address Space
BASE_ADDR + 0	address 0, bits 0-15
BASE_ADDR + 1	address 0, bits 16-31
BASE_ADDR + 2	address 0, bits 32-33
BASE_ADDR + 3	address 1, bits 0-15
BASE_ADDR + 4	address 1, bits 16-31
BASE_ADDR + 5	address 1, bits 32-33

Instead, it could be mapped as:

Bus Address Space	BRAM Address Space
BASE_ADDR + 0	address 0, bits 0-15
BASE_ADDR + 1	address 1, bits 0-15
BASE_ADDR + 2	address 2, bits 0-15
...	...
BASE_ADDR + BRAM_DEPTH + 0	address 0, bits 16-31
BASE_ADDR + BRAM_DEPTH + 1	address 1, bits 16-31
BASE_ADDR + BRAM_DEPTH + 2	address 2, bits 16-31
....	....
BASE_ADDR + 2*BRAM_DEPTH + 0	address 0, bits 32-33
BASE_ADDR + 2*BRAM_DEPTH + 1	address 1, bits 32-33
BASE_ADDR + 2*BRAM_DEPTH + 2	address 2, bits 32-33

And this would swap out the modulo (and division) operations on the FPGA for a simple 'is this address in memory bounds' check, which is just a comparision.