estija

LIME

Implementation of the paper, "LIME: Low-Light Image Enhancement via Illumination Map Estimation"

Co-VeGAN

Co-VeGAN: Complex-Valued Generative Adversarial Network for Compressive Sensing MR Image Reconstruction

RISC

Verilog implementation of the 32-bit RISC processor.

Maze-solving-line-follower

Programmed a line following bot to find the shortest path through a maze.

Verilog-assignments

This repository contains some Verilog files in which DLD concepts like adders, multiplexer, multiplier, flip-flops, encoder etc. have been implemented.

32-bit-ALU

A 32-bit ALU with carry look ahead adder and ripple carry adder and provision for signed and unsigned numbers.

CMID

Code for the Conditional Mutual Information-Debiasing (CMID) method.

Four-Way-Traffic-Control-System

LED-matrix

A project with arduino and shift registers which displays letters(moving and static) in the form of an 8x5 LED matrix.

simplicitybiaspitfalls

starter-academic

🎓 Easily create a beautiful academic résumé or educational website using Hugo, GitHub, and Netlify

estija.github.io

wilds

A machine learning benchmark of in-the-wild distribution shifts, with data loaders, evaluators, and default models.