rowanG077

clash-eth-tinytapeout

Clash ethernet MAC tinytapeout module

clash-ethernet

liteeth

Small footprint and configurable Ethernet core

yosys_ecp5_infer_bram_outreg

automated_reasoning

clash-cores-crc

Temporary repo until upstream is merged

clash-netlist-gen-bug

clash-playground

cq-flake

CadQuery and CQ-editor flake, closely follows master

ecpprog

Programmer for the Lattice ECP5 series, making use of FTDI based adaptors

ghc-aarch64-bug

ghc-typelits-extra

Extra type-level operations on GHC.TypeLits.Nat and a custom solver

ghc-typelits-natnormalise

Normalise GHC.TypeLits.Nat equations

liteeth-16-byte-bug

litescope

Small footprint and configurable embedded FPGA logic analyzer

litex

Build your hardware, easily!

nextpnr

nextpnr portable FPGA place and route tool

nixos-apple-silicon

Resources to install NixOS bare metal on Apple Silicon Macs

nixpkgs

Nix Packages collection

Open3D

Open3D: A Modern Library for 3D Data Processing

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

openlane2

The next generation of OpenLane, rewritten from scratch with a modular architecture

parallel-computing

parallel-computing-assignments

sac-cmake-common

CMake files commonly used by sac packages

sac-nix

nix files to build sac + stdlib

synlig

SystemVerilog support for Yosys

tt-gds-action

Tiny Tapeout GDS Action (using OpenLane)

udp-echo-bench

Benchmark remote UDP server

yosys

Yosys Open SYnthesis Suite

yosys-f4pga-plugins

Plugins for Yosys developed as part of the SymbiFlow project.