Test DQ-DQS in Verilator (litex_sim)

[Yimin Gao]

I am adding support to a new RISC-V core. Before adding L1 cache to the core, it works well with LiteX. (Can run litex bios, and litex demo app in dram)
After adding L1 cache, after booting the generated bitstream to FPGA, it stops here and cannot go futher.

However, things work well in Verilator (litex_sim), I can even run demo app from DRAM.
(litex_sim --cpu-type asip --with-sdram --sdram-init=demo.bin)

So I wanted to ask how I could debug in this case. If I understand correctly, the verilator doesn't include the DQ-DQS training? Is there a way that I can include that step in simulator so that I can debug the issue? Thanks!

[enjoy-digital]

Hi @YiminGao0113,

can you provide more info on the board you are using and if other CPU (ex VexRiscv) are passing the memory training correctly?

Unfortunately, as you saw, the simulation is using a simplified model of the DRAM PHY, without DQ-DQS calibration. If the SoC is working correctly with other CPU and not yours, the problem is probably related to CSR accesses. I would then recommend doing more simulations with your CPU and CSR accesses, to be sure that CSR of different size are correctly accesses. (you could try some accesses of similar size than the one done during the DRAM calibration).