Yimin Gao's repositories
ArtyS7-RPU-SoC
Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.
learn-fpga
Learning FPGA, yosys, nextpnr, and RISC-V
black-parrot
A Linux-capable RISC-V multicore for and by the world
Blog
My blog :)
ChatroomApp
🥴A web chatroom app
CS-Notes
:books: 技术面试必备基础知识、Leetcode、计算机操作系统、计算机网络、系统设计
fifo
Generic FIFO implementation with optional FWFT
firmware-syntiant-tinyml
Edge Impulse firmware for Syntiant TinyML board
github-clone-all
Clone (~1000) repos matched to query on GitHub using Search API
iverilog
Icarus Verilog
leetcode
😏 LeetCode solutions in any programming language | 多种编程语言实现 LeetCode、《剑指 Offer（第 2 版）》、《程序员面试金典（第 6 版）》题解
litex
Build your hardware, easily!
litex-boards
LiteX boards files
MiniDiscord
A mini discord server 😋
Nitro-Parts-lib-SPI
Verilog SPI master and slave
OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
serv
SERV - The SErial RISC-V CPU
SPI
SPI protocol modules in SystemVerilog
subservient
Small SERV-based SoC primarily for OpenMPW tapeout
tt06-verilog-template
Submission template for Tiny Tapeout 06 - Verilog HDL Projects
verilog-uart
Verilog UART
vimrc
The ultimate Vim configuration (vimrc)
YiminGao0113.github.io
My web page XD