elliothe

the-art-of-command-line

Master the command line, in one page

tuning_playbook

A playbook for systematically maximizing the performance of deep learning models.

llama2.c

Inference Llama 2 in one file of pure C

pandas-ai

Chat with your data (SQL, CSV, pandas, polars, noSQL, etc). PandasAI makes data analysis conversational using LLMs (GPT 3.5 / 4, Anthropic, VertexAI) and RAG.

annotated_latex_equations

Examples of how to create colorful, annotated equations in Latex using Tikz.

NyuziProcessor

GPGPU microprocessor architecture

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

rsd

RSD: RISC-V Out-of-Order Superscalar Processor

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

AutoKernel

AutoKernel 是一个简单易用，低门槛的自动算子优化工具，提高深度学习算法部署效率。

OpenRAM

An open-source static random access memory (SRAM) compiler.

vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

DDAD

Dense Depth for Autonomous Driving (DDAD) dataset.

qtrvsim

RISC-V CPU simulator for education purposes

pulp

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

cvpr-latex-template

Extended LaTeX template for CVPR/ICCV papers

awesome_ai4eda

mempool

A 256-RISC-V-core system with low-latency access into shared L1 memory.

DRAMSys

DRAMSys a SystemC TLM-2.0 based DRAM simulator.

openhls

PyTorch model to RTL flow for low latency inference

avx_mathfun

AVX-optimized sin(), cos(), exp() and log() functions

PlaneDepth

[CVPR2023] This is an official implementation for "PlaneDepth: Self-supervised Depth Estimation via Orthogonal Planes".

Interface-Protocol-in-Verilog

Interface Protocol in Verilog

sram22

A configurable SRAM generator

OpenCache

An open-source custom cache generator.

asic_labs_sp22

arche

Arche is a Greek word with primary senses "beginning". The repository defines a framework for technology mapping of emerging technologies, with primary focus on ReRAMs.

GPT-LS

NSFC-latex-template

chisel-pymtl-template

A template project for beginning new Chisel and PyMTL work