einstein07 / Vivado-IP-and-Resource-Usage

Creates a simple major arpeggiator using a Vivado IP core on a Nexys A7 FPGA board.

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arpeggiator music fpga fpga-programming verilog-hdl

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Creates a simple major arpeggiator using a Vivado IP core on a Nexys A7 FPGA board.

arpeggiator music fpga fpga-programming verilog-hdl

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Language:VHDL 96.5%Language:Verilog 2.4%Language:Coq 0.5%Language:Shell 0.3%Language:JavaScript 0.1%Language:Tcl 0.1%Language:HTML 0.1%Language:C 0.0%Language:Stata 0.0%Language:Forth 0.0%Language:Batchfile 0.0%Language:Pascal 0.0%