debtanu09

systolic_array_matrix_multiplier

This is a verilog implementation of 4x4 systolic array multiplier

my8085

This is the Verilog code for 8085 microprocessor with limited (18) number of instructions

fmultiplier

This is the verilog implementation of IEEE 754 32 bit floating point multiplier

biriscv

32-bit Superscalar RISC-V CPU

booth_multiplier

Verilog Implementation of completely parameterized booth multiplier

customrisc

This is the Verilog implementation of custom RISC ISA

des_crypto

This is the verilog implementation of DES cryptography

ee705-floating-point-multiplier

This is a repository containing all the Quartus and NIOS II simulation files and the testcases for EE705 course

fpga_counter_spartan6

FPGA implementation of up / down BCD counter

GUI_Plot

iic-audiodac-v1

Delta-sigma audio DAC (16b, 48kHz), intended for tape-out on MPW-5, SKY130 technology.

Superscalar-MIPS

A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines

debtanu09

IITB-Campus-Placement-Resumes

logpu

Lightweight OoO GPGPU

OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

pipelinedcustomrisc

Verilog implementation of a 6-stage pipelined custom RISC processor

rodinia

rodinia benchmark modified to run with ENZO and pathcu instead of nvcc CUDA compiler