debtanu09 / pipelinedcustomrisc

Verilog implementation of a 6-stage pipelined custom RISC processor

pipelinedcustomrisc

Verilog implementation of a 6-stage pipelined custom RISC processor

Verilog implementation of a 6-stage pipelined custom RISC processor

MIT License

Language:C 84.2%Language:Verilog 14.5%Language:Coq 0.4%Language:Python 0.4%Language:C++ 0.2%Language:Assembly 0.1%Language:Shell 0.1%