Banded approach of semi-global levenshtein distance on FPGA using OpenCL.
This work was published in FPL2021.
The [short] video presentation is available here:
This is a test application to test the effectiveness of our FPGA-based pre-alignment filter based on a bit parallel strategy using diagonal bit vectors. We provide the code we have used in our FPL2021 publication "as is". Improvements in the proposal will probably be uploaded to future repositories.
Prealignment filters are used to discard sequence pairs that have a higher number of errors than a given threshold.
The test main goal is to build synthetic sequences with a number of controlled errors to analyze the response of the filter in various situations.
The source code embedds the edlib (https://github.com/Martinsos/edlib/) to check the number of errors when necessary.
The application can work in two modes of operation.
-- Single Test In this mode the user provides the sequences to be compared
-- Multiple Synthetic Test In this mode the user provides the characteristics of the features that are randomly created.
| Parameter | Description |
|---|---|
| -v | verbose output |
| -pid | Identifier of the OpenCL Platform to use |
| -tl | Length of the Text |
| -pl | Length of the pattern |
| -ES | Number of Substitution Errors |
| -EI | Number of Insertion Errors |
| -ED | Number of Deletion Errors |
| -th | The error threshold |
| -N | The number of pairs to test |
| -t | The text sequence for a single test |
| -p | The pattern sequence for a single test |
filter-test -pid 0 -ES 4 -th 3 -tl 100 -pl 120 -n 10
It creates 10 sequence pairs. The text length and pattern length are all equal to 100. The pattern has 4 substitution errors compared with the text and the detection threshold is set to 3. The OpenCL platform 0 is used and the SHD algorithm is tested.
@INPROCEEDINGS{9556490,
author={Castells-Rufas, David and Marco-Sola, Santiago and Aguado-Puig, Quim and Espinosa-Morales, Antonio
and Moure, Juan Carlos and Alvarez, Lluc and Moretó, Miquel},
booktitle={2021 31st International Conference on Field-Programmable Logic and Applications (FPL)},
title={OpenCL-based FPGA Accelerator for Semi-Global Approximate String Matching Using Diagonal Bit-Vectors},
year={2021},
volume={},
number={},
pages={174-178},
doi={10.1109/FPL53798.2021.00036}}