In this project both datapath and controller of ARM Single Cycle CPU is designed by using Verilog. I implemented this on Altera De0-Nano FPGA board. Necessary modules and schematic files are added. It can process following instructions: ADD, SUB, AND, OR, LSL, LSR, LDR, STR, CMP. ARM instruction format is used. It can be further improved by changing datapath and controller according to desired instruction.
Datapath:
Example instructions:
