coldnew / zybo-templates

Basic project template for Xilinx zynq-7000 ZYBO board

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zybo-templates

Basic project template for Xilinx zynq-7000 ZYBO board

About

This project is based on Digilent/ZYBO, I keep the board file I need for different Vivado SDK.

To use this template, you must switch to the dir contains create_project.tcl, take 2018.1/linux_bd as example:

cd 2018.1/linux_bd/proj
/opt/Xilinx/Vivado/2018.1/bin/vivado -mode batch -source create_project.tcl

Then you will see following directories created by vivado

.
├── cleanup.cmd
├── cleanup.sh
├── create_project.tcl
├── linux_bd.cache
├── linux_bd.hw
├── linux_bd.ip_user_files
├── linux_bd.srcs
└── linux_bd.xpr

4 directories, 4 files

Constraints

The constraints file I used is Zybo-Master.xdc, which is taken from Digilent/digilent-xdc.

Note that I don't have Zybo Z7 board, so I can't guarantee this template can work on Zybo Z7.

Board Files

The boad files I used is zybo, which is taken from Digilent/vivado-boards.

To install the board files, just copy data/board_files/zybo to your vivado folder

cp data/board_files/* /opt/Xilinx/Vivado/2016.1/data/boards/board_files/

About

Basic project template for Xilinx zynq-7000 ZYBO board


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Language:C 56.1%Language:VHDL 20.1%Language:Tcl 11.3%Language:Verilog 9.3%Language:C++ 2.2%Language:CartoCSS 0.4%Language:Assembly 0.4%Language:Makefile 0.3%Language:Shell 0.0%Language:Batchfile 0.0%