Beast code in Giters

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

Language:VerilogNOASSERTION579 9 6

nn_playground

Experimental keras implementation of novel neural network structures

Language:PythonMIT430 25 17

AccDNN

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

Language:VerilogApache-2.0397 25 14

UVVM

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/

Language:VHDLApache-2.0371 55 198

Sora

The Microsoft Research Software Radio (Sora) is a programmable software radio platform based on the commodity multicore CPU in a host PC. The SDK provides the drivers, user mode 802.11a/b/n samples, and a debug plot tool.

Language:CNOASSERTION350 96 1

Piccolo

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

Language:VerilogApache-2.0309 24 26

bnn-fpga

Binarized Convolutional Neural Networks on Software-Programmable FPGAs

Language:CBSD-3-Clause302 36 26

STM32F4_UVC_Camera

STM32F4-Discovery USB Device UVC Camera examples

Language:C247 29 5

litex-buildenv

An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!

Language:PythonBSD-2-Clause214 24 144

GUINNESS

GUINNESS: A GUI-based binarized deep Neural NEtwork SyntheSizer toward an FPGA

Language:PythonGPL-2.0181 36 10

FPGA-CNN

FPGA implementation of Cellular Neural Network (CNN)

Language:VerilogMIT136 270

Limago

Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack

Language:TclBSD-3-Clause122 22 19

lm32

LatticeMico32 soft processor

Language:VerilogNOASSERTION102 220

litex-vexriscv-tensorflow-lite-demo

TF Lite demo on LiteX/VexRiscv soft RISC-V SoC on a Digilent Arty board

Language:RobotFrameworkApache-2.062 19 28

bnn

Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools

Language:Jupyter NotebookMIT47 3 3

Camera-Tracking

Our project is the system that enables a moving camera to track a moving object in real time. We plan on doing this by having a camera mounted to a swivel using two servo motors to allow for the camera’s direction to be controlled. The camera data will be read into the FPGA board and some basic object recognition algorithm will be used to identify an some object and determine if the camera needs to be moved to keep the object in the field of vision. In addition to the auto tracking mode, we plan on having an IR remote to allow for manual panning, mode selection, and power on and off. If there is additional time we would like to also interface the FPGA to a Raspberry Pi board running a linux web server to allow for email alerts (when object moves) and web based control.

Language:VHDL31 90

chinafpga

Chinafpga's starred repositories

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32-Verilog-Mini-Projects