bingoshu's repositories
RV12
RISC-V CPU Core
my_ecc
something about ecc,software or hardware
antikernel-ipcores
FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
ARM_documents
Documents for ARM
axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
bingoshu
Config files for my GitHub profile.
Dilithium
High-speed full CRYSTALS-DILITHIUM implementation on FPGA: Keygen, Sign, Verify.
Simple-BPNetwork
Simple BPNetwork implementation in Verilog HDL
svut
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
AhaM3SoC
SoC Based on ARM Cortex-M3
4096bit-IDDMM-Verilog
4096bit Iterative digit-digit Montgomery Multiplication in Verilog
oh
Verilog library for ASIC and FPGA designers
tvip-axi
AMBA AXI VIP
softmax
Verilog implementation of Softmax function
gen_amba_2021
AMBA bus generator including AXI4, AXI3, AHB, and APB
turtle_draw
python将图片进行边缘检测和轮廓提取进行turtle绘画
Digit-Serial-multiplier-based-on-systolic-array
Verilog implementation of digit-serial multiplier based on systolic array on GF(2^163) domain.
register-mode-dma
A register mode DMA example that demonstrates moving data from a traffic generator to DDR memory
uvm_testbench_gen
Novel GUI Based UVM Testbench Template Builder
ARM_Implementation
This repository contains an implementation of ARM processor in VerilogHDL
RSA-Montgomery-Algorithm-Hardware-implement
just a test
basic_verilog
Must-have verilog systemverilog modules
Python123
玩转python内置turtle库, 创造精美绘画
SoC_Automation
SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.
ARM9-compatible-soft-CPU-core
This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.
openofdm
Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
Verilog-SHA-Family
FPGA implementation of SHA1/SHA224/SHA256/SHA384/SHA512.