bingoshu's repositories
AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
AHB2
AMBA AHB 2.0 VIP in SystemVerilog UVM
async_mem_example
Construct async read memory from block memory in FPGA
Cache-Controller
Cache controller based on verilog with cache coherence for two processors
ComputerArchitectureLab
This repository is used to release the Labs of Computer Architecture Course from USTC
CoPHEE
CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.
cryptech
Collection of CrypTech repos to making cloning easier.
Guide-to-FPGA-Implementation-of-Arithmetic-Functions
Examples from the book by Deschamps et al. https://www.amazon.com/Implementation-Arithmetic-Functions-Electrical-Engineering/dp/9400729863
H264
H264视频解码verilog实现
HuffmanCode
hardware implement of huffman coding(written in verilog)
lisnoc
LIS Network-on-Chip Implementation
Modular_exponentiation_in_VHDL
Modular exponentiation in VHDL with Montgomery's multiplication enhanced with Karatsuba's algorithm.
montgomery_hw
KU Leuven DDP - Montgomery hardware project Group 12
OFDM-baseband
Verilog实现OFDM基带
Peppa-Pig
使用python turtle库画一只小猪佩奇
qdi-sdm-noc
A QDI spatial division multiplexing (SDM) NoC
RSA
A Montgomery modular multiplication block for a RSA module
RSA4096
4096bit RSA project, with verilog code, python test code, etc
security_stack
Set of security modules interfaced on the AXI4 bus
sha256_multicores
a sha256 hardware design with 4 lines of pipelines and use 4 cores to accelerate calculation
simple_SoC
Small and simple, primitive SoC with GPU, CPU, RAM, GPIO
SM4-SBOX
Verilog Implementation of SM4 s-box
Softmax_CNN
This repository contains full code of Softmax Layer in Verilog
stx_cookbook
Altera Advanced Synthesis Cookbook 11.0
tnoc
Network on Chip Implementation written in SytemVerilog
turbo-interleaver
两级流水线的LTE4路并行输出的turbo码交织器
turtle
使用python的turtle画樱花树，玫瑰，圣诞树，小猪佩奇，蛋糕，小黄人，贪吃蛇游戏61行代码
vdf-fpga
A low latency modulo squaring algorithm using Montgomery multiplication, submitted to the VDF FPGA design competition, targeting AWS FPGAs. Was awarded first prize for lowest latency in alternative approaches category.