Bhrigu B's repositories
university-tuition-and-ranking-correlation
Use bash to find correlation in university ranking and the tuition fees
first-contributions
🚀✨ Help beginners to contribute to open source projects
tensorflow
An Open Source Machine Learning Framework for Everyone
vscode
Visual Studio Code
serverless-stack-client-mw-sp
Serverless Amazon Stack Client MW SP
serverless-stack-api-mw-sp
mw-sp API
graduation
$ git remote <graduation> yearbook
Network-Manager
Network Manager
GasPred
Gas Price Prediction Service
kNN-based-MNIST-digit-recognition
Custom kNN based MNIST digit recognition. No built in kNN function used to process data.
ADB-data-conversion
ADS-B Exchange daily flight data json conversion and processing using R. Automated shell script to fetch data for set duration and execute R script.
Robot_MazeSolver
Win It
Sequence-detector-using-Gate-Level-modeling
Sequence detector using Gate Level modeling
Frequency-divide-by-8-circuit-using-T-Flip-Flop
Frequency divide by 8 circuit using T Flip Flop
Digital-circuit-design
Digital circuit design. After synthesis is over, modified the code so that buffer (BUF) provides a delay of 5 units, AND gate of 4 units and OR gate of 3 units. D Flip Flop has set up requirement of 3 units and hold requirement of 4 units. Used specify block for defining setup and hold requirements. Calculated the minimum time period (or maximum frequency). Provided clock input with smaller time period than required to observe setup and hold violations. Verified proper functionality of the circuit after this increase in the time period to the required value.
DFF-with-asynchronous-preset-and-reset-and-verified-for-Xilinx-Virtex-6-FPGA
DFF with asynchronous preset and reset and verified for Xilinx Virtex 6 FPGA
Design-and-Verification-of-functionality-using-Core-Generator
Using Core generator Designed and Verified functionality of following blocks i. 5x5 unsigned multiplier ii. 32x4 Simple Dual Port Ram iii. 5 Bit Adder/Subtractor Circuit using Fabric(Verify using FPGA Editor) iv. 3 Bit Adder/Subtractor Circuit using DSP48(Verify using FPGA Editor) v. 8x8 ROM with initial value provided from .coe file
Asynchronous-RAM-CY6264
Design and verify the functionality of the Asynchronous RAM CY6264
8_3-priority-encoder-using-dataflow-modeling
8_3 priority encoder using dataflow modeling
8-bit-Arithmetic-Logical-Unit
8-bit Arithmetic Logical Unit
4x4-sequential-multiplier-using-booths-algorithm
Designed 4x4 sequential multiplier using booths algorithm
32x8-Asynchronous-ROM
32x8 asynchronous ROM. Read_address and ouput_en are two inputs of ROM. Used $fmonitor to store the location(@location_in_hex) and content(conten_in_hex) that is read in mem.txt file and used $readmemh system task to: a. Initialize ROM from data stored in “memory1.txt” file. Each location stores the content equivalent to its read_ address (i.e. 5 is stored in 5th location of ROM). Used self testing test bench to verify that the content and the read_address are equal to each other for a particular location. b. Initialized ROM from data stored in “memory2.txt” file. Stored the data in address ranging from 15 to 28. Verified the content stored using test bench.
16-x-16-Synchronous-Memory
16 x 16 Synchronous Memory
16-x-16-Bidirectional-Memory
16 x 16 Bidirectional Memory
16_4-Priority-Encoder
16_4 Priority Encoder
GoPiGo3
The GoPiGo3 is a Raspberry Pi Robot!
Probability_solver
Implemented a program that computes and returns the probability of any conjunction of events given any other conjunction of events for 5 argument Bayesian network.