Digital circuit design. After synthesis is over, modified the code so that buffer (BUF) provides a delay of 5 units, AND gate of 4 units and OR gate of 3 units. D Flip Flop has set up requirement of 3 units and hold requirement of 4 units. Used specify block for defining setup and hold requirements. Calculated the minimum time period (or maximum frequency). Provided clock input with smaller time period than required to observe setup and hold violations. Verified proper functionality of the circuit after this increase in the time period to the required value.
Digital circuit design. After synthesis is over, modified the code so that buffer (BUF) provides a delay of 5 units, AND gate of 4 units and OR gate of 3 units. D Flip Flop has set up requirement of 3 units and hold requirement of 4 units. Used specify block for defining setup and hold requirements. Calculated the minimum time period (or maximum frequency). Provided clock input with smaller time period than required to observe setup and hold violations. Verified proper functionality of the circuit after this increase in the time period to the required value.