bhrigub / DFF-with-asynchronous-preset-and-reset-and-verified-for-Xilinx-Virtex-6-FPGA

DFF with asynchronous preset and reset and verified for Xilinx Virtex 6 FPGA

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DFF with asynchronous preset and reset and verified for Xilinx Virtex 6 FPGA

Language:Verilog 100.0%