bcfanny

v2ray-core

A platform for building proxies to bypass network restrictions.

opentitan

OpenTitan: Open source silicon root of trust

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

corundum

Open source FPGA-based NIC and platform for in-network compute

basic_verilog

Must-have verilog systemverilog modules

aws-fpga

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

oh

Verilog library for ASIC and FPGA designers

verilog-pcie

Verilog PCI express components

riffa

The RIFFA development repository

potato

A simple RISC-V processor for use in FPGA designs.

litex-buildenv

An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!

cocotbext-axi

AXI interface modules for Cocotb

micropython

MicroPython port package for RT-Thread

hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

app-release

An IoT Solution,this is the android release app | download ios app in app store

IPCORE

open-nic-shell

AMD OpenNIC Shell includes the HDL source files

xvc-esp32

Wireless JTAG 'cable' for Xilinx FPGAs. This is an 'English fork' of https://github.com/ciniml/xvc-esp32 project.

Open_RegModel

:hatched_chick:Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.

ethernet-fmc-axi-eth

Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks

gen_apb_file

spi-to-axi-bridge

An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

Cosmos-OpenSSD

python-pci

Python interface to PCIE

vivado-ip-cores

IP Cores that can be used within Vivado

xdma_dsc_byp_cltr

VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe

can_axi4lite

CAN-bus Controller with AXI4-lite Interface

qep-drivers

cocotb

Coroutine Co-simulation Test Bench

AXI_SPI_SLAVE