Giters
alexforencich
/
verilog-pcie
Verilog PCI express components
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Watchers:
50
Issues:
46
Forks:
264
alexforencich/verilog-pcie Issues
request for pcie axi slave verilog
Updated
3 months ago
Comments count
1
Segmented memory address bug caused by ram_mask_1_reg assertion in dma_if_pcie_rd.v
Updated
4 months ago
FPGA versus FPGA_AXI Example Questions
Updated
4 months ago
Comments count
10
Which part is the digital part of Serdes Phy?
Updated
4 months ago
Comments count
2
Standalone use
Closed
4 months ago
Comments count
2
I have two questions ,can someone help me
Updated
5 months ago
Comments count
1
Using both DMA and separate AXI Slave as PCIe requester?
Updated
8 months ago
Comments count
2
AXI dma client support?
Closed
8 months ago
Comments count
1
Implementation of PCIe “Non-Transparent Bridge" (NTB)
Updated
9 months ago
Comments count
2
What name of the Top module name of all the verilogs in rtl folder?
Updated
9 months ago
Comments count
1
About pcie_us_if
Updated
a year ago
Comments count
1
bug in dma_if_pcie_rd when max read request size is set to 4096 bytes
Updated
a year ago
Why there is no sgDMA in example_core.v
Closed
a year ago
Comments count
3
dma_read_desc_status_valid not asserted when requesting memory read length > 8
Updated
a year ago
Comments count
9
How to test pcie_us_axi_dma on board?
Updated
2 years ago
Add P-tile support
Closed
2 years ago
Comments count
1
Intel PCIe IP model
Updated
2 years ago
Comments count
3
Send immediate data to host?
Closed
2 years ago
Comments count
4
what is the purpose of ram_wr_done and how to assert it?
Closed
2 years ago
Comments count
1
Doc?
Updated
2 years ago
Comments count
1
typo in Stratix 10 shim
Closed
2 years ago
Comments count
2
unexpected dma read request logged
Closed
2 years ago
Comments count
3
Support of CXL 2.0
Updated
2 years ago
Support for Xilinx soft PCIe PHY?
Updated
2 years ago
Comments count
1
Communication between logic and host using PCIe
Closed
2 years ago
Comments count
7
64bit write/read instead of 32bit
Closed
3 years ago
Comments count
5
Add Stratix 10 GX/MX device support
Closed
3 years ago
Comments count
1
cocotb installaion commands
Closed
3 years ago
Is there a driver for window7/10?
Closed
3 years ago
Comments count
2
Module not found issue comming
Closed
3 years ago
Comments count
3
Add Arria 10 device support
Updated
3 years ago
Add support for adm-pcie-8v3
Closed
3 years ago
vivado version
Updated
4 years ago
Comments count
10
Request for U200 Support
Closed
4 years ago
Comments count
5
AU50 example fails to generate bitstream
Closed
4 years ago
Comments count
2
Example host code on top of the kernel module?
Updated
4 years ago
Comments count
24
Make failure for example VU1525/fpga_axi/driver
Closed
4 years ago
Comments count
7
pcie_disable_fatal_err.sh not working
Updated
5 years ago
Comments count
12
Package tb/pcie.py as a pip package
Closed
5 years ago
Comments count
4
Hope to support xilinx kc705 pcie2.0
Updated
5 years ago
Comments count
1