arjunrajasekharan / 16bit-Sklansky-Adder

16-bit Slansky Adder design using verilog HDL

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About

16-bit Slansky Adder design using verilog HDL

Reference Circuit

Screenshot 2021-05-14 at 17 36 36

Output

  • Test Bench

TestBenchOutput

  • GTK Waveform

GTKWave

About

16-bit Slansky Adder design using verilog HDL

License:MIT License


Languages

Language:Verilog 96.9%Language:Coq 3.1%