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alighanbari2002 / Computer-Architecture-Course-Projects

Verilog descriptions of MIPS single-cycle, multi-cycle & booth multiplier.

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booth-multipliermulti-cyclemulti-cycle-processorsingle-cyclesingle-cycle-processorcomputer-architecturemipsmips-architecturemips-assemblyverilog

Computer Architecture Course Projects

Projects for the computer architecture course at Tehran university.

Course with professor Saeed Safari

Ali Ghanbari & Mohammad Mashreghi

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Verilog descriptions of MIPS single-cycle, multi-cycle & booth multiplier.

booth-multipliermulti-cyclemulti-cycle-processorsingle-cyclesingle-cycle-processorcomputer-architecturemipsmips-architecturemips-assemblyverilog

License:MIT License

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Language:Verilog 98.4%Language:C 1.6%