akashlevy / WP-RRAM-SPICE-Model

A well-posed RRAM SPICE model implemented in Verilog-A, based on Stanford/ASU filamentary model, using code developed at UC Berkeley

WP-RRAM-SPICE-Model

This code is taken from https://arxiv.org/abs/1605.04897

Wang, Tianshi, and Jaijeet Roychowdhury. "Well-posed models of memristive devices." arXiv preprint arXiv:1605.04897 (2016).

A well-posed RRAM SPICE model implemented in Verilog-A, based on Stanford/ASU filamentary model, using code developed by UC Berkeley