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Adideb Das's repositories

vlsi_soc_verilog

Created this repository with reference to VLSI SoC Design using Verilog HDL by Maven Silicon

Language:Verilog000

uvm_riscv

Language:SystemVerilog000

riscv_uvm

Language:SystemVerilog000

single_cycle_cpu

Language:VerilogMIT000

simple_dual_port_ram

Language:Verilog000

fifo_module

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rebek-007

GPL-2.0000

verilog_codes

Language:Verilog100

opencv_tutorials

Language:Python000

pihole

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Sailing-Downstream

This repository is used for the coding task "Sailing Downstream"

Language:OCaml000

remote-controlled-car

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opencv-freecodecamp

Learn OpenCV in 4 Hours - Code used in my Python and OpenCV course on freeCodeCamp.

MIT000

riscv-based-cpu

Language:Verilog000

multi-cycle-cpu

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logicgates

Language:Verilog000

riscv_model1

MIT000

smitrv

An implementation of RISC-V based core from SMIT

Language:PythonMIT000

riscvisa_ifu

Language:VerilogGPL-3.0100

riscv_cpu_core

Language:VerilogGPL-3.0000

scoppyproject

GPL-3.0000

RISCV_CPU

32 bit Base RISCV Simulator

GPL-3.0000

scoppy

Use your Rasperry Pi Pico and Android Phone as an Oscilloscope and Logic Analyzer

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