Following are the verilog code for all seven logic gates( AND, OR , NOT, NAND, NOR , XOR, XNOR)
To deploy this project clone this github repository and extract the files to VS Code.
Navigate to the particular logic gate folder and open a new terminal window
iverilog -o sim xxx_gate_tb.v
where sim is the simulation output and xxx is either of the seven logic gates.
If you wish to simulate the timing diagram of AND gate , enter
iverilog -o sim and_gate_tb.v
A simulation output of sim is created as the output file . To generate the timing diagram of sim , enter
vvp sim
A timing diagram of xxx_gate.vcd will be generated as timing diagram file. We can view it in GTKWave using the following command
gtkwave xxx_gate.vcd
If we wish to simulate AND gate , then following command is given
gtkwave and_gate.vcd
A timing diagram will be generated by GTKwave Analyser. We can analyse the output signals as per our requirement.