abhinavhimanshu / Real_time_Sobel_edge_detector

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-constraint folder contains the constraint file
-Implementation Reports system level contains the system level implementaion report
-src codes contains all the source code of this projects,heriarchy of code is described in image code_heriarchy
-test_bench contains the testbench and input test vector and refrences, It also has readme file explaining the details on how to use
-UART_SEND_CODE contains the code used to send image to FPGA using UART
-vivado_project contains system level vivado synthesis and implementaiton of project
-scripts folder contains all the scripts and has readme inside explaining everything in more details.
-Result folder contains resulting images obtained from our HW architecture

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Language:VHDL 89.5%Language:Verilog 7.7%Language:SystemVerilog 1.5%Language:Shell 0.3%Language:Tcl 0.3%Language:JavaScript 0.2%Language:HTML 0.2%Language:Coq 0.2%Language:MATLAB 0.1%Language:Stata 0.0%Language:Batchfile 0.0%Language:Pascal 0.0%Language:Forth 0.0%Language:1C Enterprise 0.0%