This is one of the three project for BSc thesis at Politecnico di Milano.
The related course for this project is "Reti Logiche" (aka Digital Devices).
Aim of this project was to realize a VHDL implementation of a Working-zone encoding method for FPGA devices.
See specification here: Specification document (italian only).
My implementation is more focused on performance and speed rather than low space consumption.
See more on my documentation (italian only).
More on Working-zone encoding topic below:
E. Musoll, T. Lang and J. Cortadella, "Working-zone encoding for reducing the energy in microprocessor address buses," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6, no. 4, pp. 568-572, Dec. 1998.